GPU Power Reduction Demo Suite

Runnable demos that simulate and analyse hardware-level techniques used to reduce GPU compute power — from RTL clock gating to INT8/INT4 quantisation and DVFS optimisation.

All Python demos run on any machine with no GPU required. The Verilog demos need Icarus Verilog and Yosys (both free, macOS/Linux).

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Demo Overview

#	File	Technique	Key Result
1	python/01_power_model.py	Pdyn = α·C·V²·f model	All-techniques combined: −96% power
2	python/02_precision_quantization.py	FP32 → FP16 → INT8 → INT4	Memory −75%, INT4 theoretical 8× throughput
3	python/03_sparsity_24.py	NVIDIA Ampere 2:4 structured sparsity	50% zeros, memory −37.5%, GPU throughput 2×
4	python/04_clock_gate_sim.py	RTL switching-activity simulation	Toggle count −35% → power −35%
5	python/05_dvfs_optimizer.py	P-State DVFS optimiser	Train→infer→idle scenario −24% energy
6	python/06_yosys_area_report.py	Yosys synthesis area analysis	INT8→INT4: cells −48%, XOR gates −54%

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Verilog Modules (synthesisable RTL)

File	Description
verilog/mac_synth.v	INT8 / INT4 / Vec4 / Precision-selectable MAC — Verilog-2005, Yosys-compatible
verilog/mac_unit.sv	Same MAC in full SystemVerilog (for Icarus / Verilator)
verilog/tb_mac_unit.sv	Testbench: 8 test cases, all pass, exports dump.vcd
verilog/clock_gate_compare.sv	Side-by-side ICG vs. non-gated register + testbench
verilog/power_domain.upf	UPF power-domain definition (Synopsys DC / Cadence Genus)
verilog/synth.ys	Yosys synthesis script for area comparison

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Yosys Synthesis Results

Module                  Wire Bits   Cells   vs INT8   Power Index
─────────────────────────────────────────────────────────────────
INT8 MAC                  1 095      741     1.00×      1.00×
INT4 MAC                    496      389     0.52×      0.32×   ← −48% area, −68% power
Vec4 INT8 MAC             4 139    2 704     3.65×     11.65×
Precision MAC (INT8+INT4) 1 730    1 166     1.57×      2.21×

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Quick Start

Prerequisites

# macOS
brew install icarus-verilog verilator yosys
pip install numpy tabulate

# Ubuntu / Debian
sudo apt install iverilog verilator yosys
pip install numpy tabulate

Run all Python demos

python3 run_all.py          # all 5 demos
python3 run_all.py 3        # demo 3 only

Run Verilog testbenches

cd verilog

# MAC unit (8 tests, exports dump.vcd)
iverilog -g2012 -o tb_mac.vvp tb_mac_unit.sv mac_unit.sv && vvp tb_mac.vvp

# Clock gating comparison
iverilog -g2012 -o tb_cg.vvp clock_gate_compare.sv && vvp tb_cg.vvp

# Yosys synthesis area analysis
yosys synth.ys

View waveform

# Online (no install): https://app.surfer-project.org/  ← upload dump.vcd
# macOS
brew install --cask surfer && surfer verilog/dump.vcd

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Project Structure

gpu_power_demo/
├── run_all.py                        Entry point
├── requirements.txt
├── python/
│   ├── 01_power_model.py             Pdyn = α·C·V²·f formula simulation
│   ├── 02_precision_quantization.py  FP32/FP16/INT8/INT4 error & speed
│   ├── 03_sparsity_24.py             2:4 structured sparsity (Ampere)
│   ├── 04_clock_gate_sim.py          RTL flip-flop toggle simulation
│   ├── 05_dvfs_optimizer.py          P-State power/perf frontier
│   └── 06_yosys_area_report.py       Synthesis area analysis report
└── verilog/
    ├── mac_synth.v                   Yosys-compatible MAC (Verilog-2005)
    ├── mac_unit.sv                   Full SV MAC + precision MUX
    ├── tb_mac_unit.sv                Testbench (7/7 pass)
    ├── clock_gate_compare.sv         ICG cell RTL + testbench
    ├── power_domain.upf              UPF power domain spec
    └── synth.ys                      Yosys synthesis script

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Code Improvement Roadmap

Priority	Technique	Impact
P1	Operand isolation (a_iso = enable ? a : 0)	−15–30% glitch power, 3-line change
P2	Accumulator width reduction (ACC_W = clog2(MAX)+1)	Fewer DFF cells
P3	1-stage pipeline register	Frequency 450 → 600+ MHz
P4	Multiplier sharing across INT8/INT4 paths	−20% area in Precision MAC
P5	Real stdcell library (abc -liberty sky130.lib)	−25–40% area vs generic gates

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Tool Stack

Tool	Purpose	Cost
Icarus Verilog	Verilog simulation	Free
Verilator	Fast cycle-accurate simulation	Free
Yosys	RTL synthesis & area analysis	Free
Surfer	Waveform viewer	Free
Synopsys Design Compiler	Production ASIC synthesis	Commercial
Cadence Joules	RTL power analysis	Commercial